1. Field of the Invention
The present invention relates to a process for forming electrodes for semiconductor devices, and more particularly to a process for forming an electrode for providing an electrical connection between an external circuit and an electrically conductive portion of the semiconductor device such as a metal wiring layer protectively covered by an electrically insulating coating.
2. Description of the Prior Art
When a semiconductor device having its surface covered by an electrically insulating coating is subjected to failure analysis, an analyzing electrode electrically connected to the internal circuit of the semiconductor device must frequently be newly formed on the electrically insulating protective coating. A semiconductor device to be analyzed may not have been provided with external lead terminals or bonding pads, or even if the semiconductor device has external lead terminals or bonding pads, it may be difficult to obtain a satisfactory failure analysis merely by utilizing the incoming/outgoing signals passing through the external lead terminals or the bonding pads. In these cases, if electrical signals are to be transmitted to and received from the internal circuit of the semiconductor device, it becomes particularly necessary to form such an analyzing electrode.
When an electrically conductive portion such as metal wiring constituting a part of the semiconductor device has a large pattern size or the interval between two adjacent patterns is large, the metal wiring may be exposed by partially or completely removing the electrically insulating protective coating of the semiconductor device. Subsequently, if a probe is directly brought into contact with the thus-exposed metal wiring, electrical signals can be transmitted to and received from the internal circuit of the semiconductor device for analyzing purposes.
Recently, however, as semiconductor devices have become increasingly integrated and more complicated, the pattern size of their metal wiring and the interval between adjacent patterns have been reduced to a significant extent. Therefore, such a size or interval is far smaller than the tip diameter of the probe, and this may cause various difficulties; for example, the tip of the probe may cause damage to the metal wiring during failure analysis This makes it difficult to subject semiconductor devices to failure analysis. To cope with this problem, the following prior-art process has been utilized. In the conventional process which will be described later, an analyzing electrode having a size larger than the tip diameter of the probe is formed on the electrically insulating protective coating of a semiconductor device, with the analyzing electrode electrically connected to the internal circuit of the device. In order to transmit and receive electrical signals to and from the internal circuit of the device, a probe is brought into contact with the thus-formed analyzing electrode.
FIGS. 5A to 5E are respectively diagrammatic, cross sections used for explaining a process sequence for forming an electrode for a semiconductor device according to the prior art. The prior-art process for forming an electrode will be described below with reference to FIGS. 5A to 5E.
Referring first to FIG. 5A, a semiconductor substrate of one conductivity type is indicated at 110, and includes a source (or drain) 121 and a drain (or source) 122 both of which are formed as impurity-diffused regions. P-n junctions 131 and 132 are respectively formed at the boundary between the source (or drain) 121 and the substrate 110 as well as that between the drain (or source) 122 and the substrate 110. The substrate 110 partially serves as a channel region for providing an electrical connection between the source (or drain) 121 and the drain (or source) 122. A gate oxide film 123 is formed on the portion of the substrate 110 that forms such a channel region, and a gate electrode 124 is further formed on the film 123, thereby constituting a MOS transistor 120. Metal wires 1 each serving as an electrically conductive portion are respectively connected to the gate electrode 124, the source (or drain) 121 and the drain (or source) 122. An isolation film 140 electrically isolates the metal wires 1 from the substrate 110 as well as thew metal wires 1 from one another. The entire surface of the semiconductor device having the aforesaid arrangement is covered by an electrically insulating protective coating 2 serving as an isolation layer so that the device surface may be smoothed and at the same time the semiconductor device may be protected from contamination.
As shown in FIG. 5A, in order to dispose an analyzing electrode on the thus-formed semiconductor device, a converged ion beam 3 is locally irradiated onto the portion of the electrically insulating protective coating 2 overlying a connecting portion 11 of the metal wire 1 to which the analyzing electrode is to be connected.
Referring to FIG. 5B, the constituent atoms of the thus-irradiated portion of the electrically insulating protective coating 2 are scattered by the phenomenon of sputtering through irradiation of the converged ion beam 3, and to thus bore into the irradiated portion.
As shown in FIG. 5C, this boring is continued until the desired portion of the metal wire 1 is exposed, that is, to a depth required for electrical connection. Thus, a predetermined opening is formed in the electrically insulating protective coating 2.
Referring to FIG. 5D, while a gaseous or vaporized metal compound 31, which can be decomposed to generate a metal through irradiation of a converged ion beam, is being supplied to an area which includes a portion to be bored, i.e., the connecting portion 11 and which corresponds to the shape and size of an analyzing electrode to be formed, this area is also being irradiated with the converged ion beam 3 to cause decomposition of the metal compound 31, thereby forming a film 6.
After the film 6 having a predetermined shape, size and thickness has been formed, the irradiation of the converged ion beam 3 and the supply of the metal compound 31 are stopped. As shown in FIG. 5E, the metal film 6 obtained in this final step serves as an analyzing electrode 4.
However, the aforesaid prior-art process for forming an analyzing electrode involves the following disadvantages which will be described below with reference to FIGS. 6A to 6C.
FIG. 6A is a diagrammatic, cross section used for explaining the disadvantages of the prior-art process for forming an analyzing electrode for a semiconductor device.
Referring to FIG. 6A, Cm represents the electrical capacitance which is produced between the substrate 110 and the metal wire 1 to which the analyzing electrode 4 is to be connected, that is before the electrode 4 has been formed. Ce represents the electrical capacitance which is produced between the substrate 110 and the analyzing electrode 4 including the metal wire 1 to which the electrode 4 is finally connected, that is after the electrode 4 has been formed on the metal wire 1. Ib represents the ion current of the converged ion beam 3. Te represents the ion irradiation period which is required to form the analyzing electrode 4 on the protective coating 2 by irradiating the metal film 6 with the converged ion beam 3 while the metal compound 31 is being supplied. Ve represents the potential difference between the substrate 110 and the analyzing electrode 4 including the metal wire 1. Vt represents the critical potential difference Ve which causes breakdown of the semiconductor device, that is, the value of withstand voltage. Also, secondary electrons generated through irradiation of the converged ion beam 3 are indicated by 32.
After the electrically insulating protective coating 2 has been bored until the desired portion of the metal wire 1 is exposed, the metal compound 31 is decomposed through irradiation of the converged ion beam 3. The analyzing electrode 4 is formed by growing the thus-generated metal film 6 in an area which corresponds to the predetermined shape and size of the analyzing electrode 4 and which includes the bored portion, i.e., the connecting portion 11. In the meantime, the ion current Ib of the converged ion beam 3 is incident upon the metal wire 1. The flow of the ion current Ib upon the metal wire 1 continues until the metal film 6 reaches a predetermined shape, size and thickness to form the analyzing electrode 4. Accordingly, after the ion irradiation period Te has elapsed, that is, when the formation of the analyzing electrode 4 is complete, the quantity of electric charge Qe supplied to the metal wire 1 becomes Qe =Ib . Te, and the potential difference Ve between the metal wire 1 and the substrate 110 becomes Ve=Qe/Ce. Therefore, even if the ion current Ib, the ion irradiation period Te of the converged ion beam 3 and the quantity of electric charge Qe are respectively the same, as the electrical capacitance Ce becomes smaller, the potential difference Ve becomes larger.
However, in highly integrated semiconductor devices, the electrical capacitance Cm is relatively small because of the extremely reduced pattern sizes of, for example, the MOS transistor 120, the source (or drain) 121, the drain (or source) 122, the gate electrode 124, the metal wires 1 and other constituent elements. Also, since the gate oxide film 123 is extremely reduced in thickness, the withstand voltage Vt of the gate oxide film 123 is of a low level. Since the interval between the substrate 110 and the analyzing electrode 4 is greater than the thickness of the gate oxide film 123, the electrical capacitance between the substrate 110 and the electrode 4 is relatively small and the electrical capacitance Ce including the aforesaid capacitance Cm is also relatively small. In the case of such small electrical capacitance Ce, if the quantity of electric charge Qe based on ordinary levels of Ib and Te is supplied to the metal wire 1, the potential difference Ve readily exceeds the level of the withstand voltage Vt. This may result in the breakdown of the semiconductor device.
As an example, if the analyzing electrode 4 having a size which allows the tip of an ordinary type of probe to be brought into contact with the electrode 4, for example, a square form with each side 80 to 120 um long, is to be formed in accordance with the aforesaid process, almost all semiconductor devices will be broken before an analyzing electrode with such a size can be formed.
In such cases, in order to prevent the occurrence of breakdown in the semiconductor devices, the size of the analyzing electrode 4 may be enlarged to increase the value of Ce. However, if the size is enlarged, the ion irradiation period Te is extended to increase the values of Qe and Ve, thereby causing the level of Ve to exceed that of Vt. This may also result in the breakdown of the semiconductor device.
In particular, since the converged ion beam 3 is commonly a beam of positive ions, a secondary ion current Ise of the secondary electrons 32 produced through irradiation of the converged ion beam 3 flows in the same direction as that of the ion current Ib. Therefore, the potential difference Ve becomes Ve=(Ib+Ise).multidot.Te/Ce, and exceeds the previously-mentioned level of Ve. In consequence, it becomes even easier for the semiconductor device to breakdown.
More specifically, referring to another example shown in FIG. 6B, while the converged ion beam 3 is being irradiated until the metal film 6 having a predetermined shape, size and thickness is obtained, the potential at the gate electrode 124 which is electrically connected to the metal wire 1 and the metal film 6 exceeds the level of withstand voltage of the gate oxide film 124 to cause dielectric breakdown of the gate oxide film 124. This results in the failure of the MOS transistor 120.
Referring to the other example shown in FIG. 6C, the potential at the source (or drain) 121 electrically connected to the metal wire 1 exceeds the level of withstand voltage of the p-n junction to cause breakdown of the p-n junction 131, and thus results in the failure of the MOS transistor 120.
As described above, use of the prior-art process for forming an electrode easily causes breakdown of a semiconductor device to be analyzed, and this may lead to the problem that correct failure analysis can not be performed.